Omkar Bhilare

I am a first-year MASc (Master of Applied Science) student at the University of Toronto, working under the guidance of Professor Jason Anderson. CGRAs are a type of reconfigurable device known for their potential to deliver greater performance gains compared to other reconfigurable hardware, such as FPGAs. My current research focuses on developing various CAD mapping algorithms for CGRAs to enable efficient application execution and maximize hardware performance.

Before starting my master's, I worked as a Silicon Design Engineer at AMD in India. During my undergraduate studies in Electronics, I interned with Prof. Paolo Ienne at EPFL for the Dynamatic project, Prof. Kamakoti at IIT Madras on the Shakti project, and participated in the Google Summer of Code with BeagleBoard.org for the BeagleWire project. I am always open to research opportunities in Computer Architecture, Reconfigurable Computing, and RTL Design & Verification. Feel free to connect with me if you would like to discuss any ideas or any of my previous work.

In my free time, I like to play cricket, chess, and watch movies.

news

Dec 15, 2023	2023 Fall Work Presentation
Apr 24, 2022	Received a sample Arty A7-35T for PipelineC Project
Jan 21, 2022	Got Accepted in the Summer EPFL Program @ LAP Lab

latest posts

Jan 25, 2022	Summer EPFL Offer from LAP LAB
Aug 01, 2021	BeagleWire · Software for BeagleWire FPGA
Jul 30, 2021	Report of Verification Intern at SHAKTI

selected publications

Hardware-Software
DEEPFAKE CLI: Accelerated Deepfake Detection Using FPGAs

Omkar Bhilare , Rahul Singh , Vedant Paranjape, and 3 more authors

In Parallel and Distributed Computing, Applications and Technologies , 2023

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Because of the availability of larger datasets and recent improvements in the generative model, more realistic Deepfake videos are being produced each day. People consume around one billion hours of video on social media platforms every day, and that’s why it is very important to stop the spread of fake videos as they can be damaging, dangerous, and malicious. There has been a significant improvement in the field of deepfake classification, but deepfake detection and inference have remained a difficult task. To solve this problem in this paper, we propose a novel DEEPFAKE C-L-I (Classification - Localization - Inference) in which we have explored the idea of accelerating Quantized Deepfake Detection Models using FPGAs due to their ability of maximum parallelism and energy efficiency compared to generalized GPUs. In this paper, we have used light MesoNet with EFF-YNet structure and accelerated it on VCK5000 FPGA, powered by state-of-the-art VC1902 Versal Architecture which uses AI, DSP, and Adaptable Engines for acceleration. We have benchmarked our inference speed with other state-of-the-art inference nodes, got 316.8 FPS on VCK5000 while maintaining 93% Accuracy.
@inproceedings{10.1007/978-3-031-29927-8_4, author = {Bhilare, Omkar and Singh, Rahul and Paranjape, Vedant and Chittupalli, Sravan and Suratkar, Shraddha and Kazi, Faruk}, editor = {Takizawa, Hiroyuki and Shen, Hong and Hanawa, Toshihiro and Hyuk Park, Jong and Tian, Hui and Egawa, Ryusuke}, title = {DEEPFAKE CLI: Accelerated Deepfake Detection Using FPGAs}, booktitle = {Parallel and Distributed Computing, Applications and Technologies}, year = {2023}, publisher = {Springer Nature Switzerland}, address = {Cham}, pages = {45--56}, google_scholar_id = {u5HHmVD_uO8C}, url = {https://www.hackster.io/thematrix/deepfakes-c-l-i-on-vck5000-f04ca2}, doi = {10.1007/978-3-031-29927-8_4}, isbn = {978-3-031-29927-8} }
Hardware-Software
CAD Techniques for NoC-Connected Multi-CGRA Systems

Haron Wei , Omkar Bhilare , Hamas Waqar, and 1 more author

In Highly Efficient Accelerators and Reconfigurable Technologies (HEART) , 2024

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Coarse-grained reconfigurable arrays (CGRAs) are programmable hardware platforms that are a means of realizing application accelerators. A CGRA is a 2D array of configurable processing elements (PEs), that connect to one another through programmable interconnects. PEs and interconnects in CGRAs are configurable at the word level, as opposed to at the bit level in FPGAs. A network-on-chip (NoC) is an on-chip communications system comprising routers and links, where data is packet-switched. NoCs provide more scalable communication vs. traditional on-chip busses or crossbars. In this paper, we propose an NoC-connected multi-CGRA system, where multiple modest-sized CGRAs communicate using an NoC. We introduce CAD techniques that partition and place an application across the “distributed” NoC-connected CGRAs. We study the quality and runtime of the CAD techniques on a system having sixteen 4 × 4 CGRAs connected together using a 2D mesh NoC.
@inproceedings{10.1145/3665283.3665297, author = {Wei, Haron and Bhilare, Omkar and Waqar, Hamas and Anderson, Jason}, title = {CAD Techniques for NoC-Connected Multi-CGRA Systems}, booktitle = {Highly Efficient Accelerators and Reconfigurable Technologies (HEART)}, year = {2024}, url = {https://camps.aptaracorp.com/ACM_PMS/PMS/ACM/HEART24/14/ed351247-1874-11ef-8182-16bb50361d1f/OUT/heart24-14.html}, doi = {10.1145/3665283.3665297}, }